Fully-depleted devices such as fin field effect transistors (finFETs) are leading candidates to enable the scaling of gate lengths to 25 nm and below. However, one challenge in realizing finFETs is increased contact resistance. The contact resistance increases when the contact is made smaller. Thus, the contact resistance increases as gate-to-gate distance is scaled down to increase density (i.e., contacted gate pitch (CPP) scaling). A conventional finFET has 1.5 times the contact resistance of a planar device of the same area. Another challenge is a 3D penalty. A conventional finFET has a 3D penalty if only the top of the fin has silicide because the current has to travel vertically from bottom to top.